The present invention relates to complex signal processing systems in which multiple components are controlled through a serial bus, and to integrated circuits which can be easily assembled into such systems.
In complex signal processing systems, commonly comprising a plurality of integrated circuits (ICs) containing functional signal processing circuits, the practice of controlling the operation of the system by a microprocessor is becoming more and more common. The microprocessor is capable of receiving and carrying out instructions for enabling/disabling certain functions and/or for adjusting certain operating parameters and of transmitting commands to the various integrated circuits for signal processing through a connection bus. Audio signal processing systems in TV receivers, car radios and similar apparatuses, make extensive use of such a microprocessor control system for selecting modes of operation for adjusting balance, tone, volume, etc.
Transmission of different control signals through the bus from the microprocessors to the various integrated circuits of the system takes place according to a certain transmission protocol. The transmission protocols more widely employed for these purposes are the so-called SPI protocol, which has been widely adopted as a standard in the U.S., and the I2CBUS protocol, which is the standard most commonly adopted in European countries:
The SPI standard requires three wires for transmitting to an interface circuit of an integrated device three distinct signals that are commonly referred to by the acronyms: CL (clock), DA (data) and CE (chip-enable). This standard does not require the selection of an address.
By contrast, the I2CBUS standard requires two wires, for transmitting the signals: CL and DA, respectively, plus the selection of an internal address (i.e. an address present within a controlled IC).
Normally, commercial ICs are specifically designated for use with one or the other of these standard protocols.
In either case, the devices are provided with three dedicated pins. In case of ICs destined to be used in an SPI environment, the IC is provided with pins CE, DA and CL. In case of devices destined to operate in an I2CBUS environment, each IC is provided with three dedicated pins, respectively, DA, CL and ADDR. The third pin ADDR of these devices is provided for address selection. Commonly, users of these ICs require the availability within each IC of at least two addresses that may be selected through said third pin ADDR.
Thus there is a burden, in terms of production management by ICs manufacturers, deriving from the necessity of producing specific devices destined to work with one or the other of said two widely adopted transmission protocols for the control data of a supervising microprocessor. There is also a burden on users, such as manufacturers of audio systems, due to the management of different inventories of ICs for producing systems according to one or the other protocol standard.
According to the disclosed innovations, these management burdens and drawbacks may be eliminated by providing ICs with a bus interface circuit for the transmission of commands from a supervising microprocessor to the functional circuit for signal processing integrated in the device, which is capable of automatically adapting itself to one or to the other of two transmission protocol standards without requiring any configuring command. The interface circuit of the instant invention is capable of assessing whether the type of transmission protocol being used differs from a "basic" standard protocol, and consequently, if the incoming control signals are transmitted according to a protocol different from said standard protocol, to simulate an operation according to said "basic" standard protocol.
Such an ability of the interface circuit object of the present invention to self-adapt itself in function of the control signals that are received through three pins of the IC is attained by applying to a third one of said three dedicated pins (for example to the ADDR pin) of the integrated circuit, the signal CE (e.g. by connecting said ADDR pin to a third wire of the transmission bus), in order to permit the functioning of the interface circuit according to an SPI protocol. Alternatively, by maintaining floating or by connecting to a ground potential said third pin ADDR, thus selecting one or the other of two internal addresses, the IC may function according to an I2CBUS protocol.
A correct operation of the interface circuit in either case (and therefore the possibility of employing the same IC in either one or the other environment) is ensured by transmitting either the CE signal that is received through the third pin ADDR in case of an SPI environment or a "virtual" CE signal that is purposely generated by the interface circuit itself in case the IC must be used in an I2CBUS environment, through a multiplexer to an inner interface block, which is substantially an SPI interface circuit.